• DocumentCode
    2048059
  • Title

    Hierarchy based statistical fault simulation of mixed-signal ICs

  • Author

    Devarayanadurg, Giri ; Goteti, Prashant ; Soma, Mani

  • Author_Institution
    Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
  • fYear
    1996
  • fDate
    20-25 Oct 1996
  • Firstpage
    521
  • Lastpage
    527
  • Abstract
    In this work we present a behavioral fault simulation technique for mixed-signal ICs, wherein a robust function approximation method namely regression splines are applied to automatically extract behavioral block parameters. The use of these robust high-level functions enables true behavioral fault simulation while preserving the statistical dependence on the process tolerance. We demonstrate significant speed-up over traditional Monte Carlo methods for two typical mixed-signal circuits, a sigma-delta modulator and a PLL
  • Keywords
    Monte Carlo methods; circuit analysis computing; integrated circuit modelling; mixed analogue-digital integrated circuits; modulators; phase locked loops; sigma-delta modulation; splines (mathematics); statistical analysis; Monte Carlo methods; PLL; VCO; behavioral fault simulation; differential integrator; high-level functions; mixed-signal IC; regression splines; robust function approximation; sigma-delta modulator; statistical fault simulation; Analytical models; Central Processing Unit; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Costs; Monte Carlo methods; Phase locked loops; Robustness;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Conference, 1996. Proceedings., International
  • Conference_Location
    Washington, DC
  • ISSN
    1089-3539
  • Print_ISBN
    0-7803-3541-4
  • Type

    conf

  • DOI
    10.1109/TEST.1996.557077
  • Filename
    557077