Title :
Structural search for RTL with predicate learning
Author :
Parthasarathy, G. ; Iyer, M.K. ; Cheng, K.-T. ; Brewer, F.
Author_Institution :
Dept of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
Abstract :
The authors presented an efficient search strategy for satisfiability checking on circuits represented at the register-transfer-level (RTL). The authors used the RTL circuit structure by extending concepts from classic automatic test-pattern generation (ATPG) algorithms and interval-arithmetic to guide the search process. The idea of Boolean recursive learning was extended on predicate logic in the RTL using Boolean and interval constraint propagation in the control and data-path of the circuit. This is used as a pre-processing step to derive relations between predicate logic signals that are used to augment the search. It is demonstrated experimentally that these methods provide significant improvement over current techniques on sample benchmarks.
Keywords :
Boolean functions; automatic test pattern generation; formal verification; Boolean recursive learning; automatic test pattern generation; interval arithmetic; predicate abstraction; predicate learning; predicate logic; register transfer level; satisfiability checking; search process; structural search; Arithmetic; Automatic control; Automatic test pattern generation; Automatic testing; Boolean functions; Circuit testing; Logic circuits; Logic design; Permission; Registers;
Conference_Titel :
Design Automation Conference, 2005. Proceedings. 42nd
Print_ISBN :
1-59593-058-2
DOI :
10.1109/DAC.2005.193851