Title :
Influence of TEOS/Si3N4 passivation layer on the performance of MOSFET/ISFET structure
Author :
Noh, Nurul Izzati Mohammad ; Yusof, Khairul Aimi ; Abdullah, Ali Zaini ; Herman, Sukreen Hana ; Abdullah, Wan Fazlida Hanim
Author_Institution :
Fac. of Electr. Eng., Univ. Teknol. MARA, Shah Alam, Malaysia
Abstract :
This paper presents an investigation of dual passivation layer deposition on the characteristic of MOSFET/ISFET structure. PECVD TEOS oxide and LPCVD Silicon nitride (Si3N4) has been used as the passivation layer and deposited on the metal shield layer of ISFET. The Keithley 236 Parameter Analyzer and Semi-auto prober micromanipulator system was used to measure the drain-source current (IDS) versus gate to source voltage (VGS) characteristics. In this study, unpassivated and passivated structure were characterized and compared. The negative shift of threshold voltage, VTH is observed after passivation layer was deposited. This might be due to the charge trapping of electrons or deposition process of passivation layer.
Keywords :
MOSFET; ion sensitive field effect transistors; organic compounds; passivation; plasma CVD; silicon compounds; Keithley 236 parameter analyzer; LPCVD silicon nitride; MOSFET/ISFET Structure; PECVD TEOS oxide; Si3N4; TEOS/Si3N4 passivation layer; drain-source current; dual passivation layer deposition; electron charge trapping; metal shield layer; semiauto prober micromanipulator system; source voltage characteristics; threshold voltage; Isothermal processes; Logic gates; MOSFET; Passivation; Semiconductor device measurement; Temperature measurement; Threshold voltage; Tetra-ethoxy-silane (TEOS); passivation layer; silicon nitride;
Conference_Titel :
Control and System Graduate Research Colloquium (ICSGRC), 2013 IEEE 4th
Conference_Location :
Shah Alam
Print_ISBN :
978-1-4799-0550-8
DOI :
10.1109/ICSGRC.2013.6653291
