Top-down design using cycle based simulation: an MPEG A/V decoder example

Author

Hocevar, Dale E. ; Hung, Ching-Yu ; Pickens, Dan ; Sriram, Sundararajan

Author_Institution

DSPS R&D Center, Texas Instrum. Inc., Dallas, TX, USA

fYear

1998

fDate

19-21 Feb 1998

Firstpage

400

Lastpage

405

Abstract

This paper presents a discussion of a top-down VLSI design approach which involves system level performance modeling, block level cycle based simulation, RTL/VHDL simulation and gate level emulation. An MPEG-2 audio/video decoder design example illustrates the use of this top-down approach. Most of the discussion concentrates on the concept of block level cycle based (BLCB) simulation. HW/SW co-design also played an important role in this work and our approach towards such co-design is discussed as well

Keywords

VLSI; decoding; digital simulation; hardware description languages; high level synthesis; integrated circuit design; HW/SW co-design; MPEG A/V decoder; MPEG-2; RTL/VHDL simulation; VLSI design approach; block level cycle based simulation; gate level emulation; system level performance modeling; top-down design; Auditory displays; Clocks; Computational modeling; Decoding; Digital signal processing; Emulation; Hardware; Logic; Read only memory; Research and development; SDRAM; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI, 1998. Proceedings of the 8th Great Lakes Symposium on

Conference_Location

Lafayette, LA

ISSN

1066-1395

Print_ISBN

0-8186-8409-7

Type

conf

DOI

10.1109/GLSV.1998.665333

Filename

665333