DocumentCode
2048885
Title
A genetic algorithm for constrained via minimization
Author
Tang, Maolin ; Eshraghian, Kanlran ; Cheung, Hon Nin
Author_Institution
Centre for Very High Speed Microelectron. Syst., Edith Cowan Univ., Joondalup, WA, Australia
Volume
2
fYear
1999
fDate
1999
Firstpage
435
Abstract
Constrained via minimization is a typical optimization problem in very large scale integrated circuit (VLSI) routing. It is used to minimize the number of vias introduced in a VLSI routing. The first genetic algorithm for the constrained via minimization problem is proposed. Experimental results show that the developed genetic algorithm can consistently produce the same or better results than the best deterministic constrained via minimization algorithms
Keywords
VLSI; circuit CAD; genetic algorithms; graph theory; minimisation; network routing; search problems; VLSI routing; constrained via minimization; deterministic algorithms; genetic algorithm; optimization problem; very large scale integrated circuit; Circuit optimization; Fabrication; Genetic algorithms; Integrated circuit yield; Large-scale systems; Microelectronics; Minimization methods; Routing; Very large scale integration; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Neural Information Processing, 1999. Proceedings. ICONIP '99. 6th International Conference on
Conference_Location
Perth, WA
Print_ISBN
0-7803-5871-6
Type
conf
DOI
10.1109/ICONIP.1999.845634
Filename
845634
Link To Document