DocumentCode
2049169
Title
Partial scan flip flop selection for simulation-based sequential ATPGs
Author
Corno, Fulvio ; Prinetto, Paolo ; Rebaudengo, Maurizio ; Reorda, Matteo Sonza
Author_Institution
Dipt. di Autom. e Inf., Politecnico di Torino, Italy
fYear
1996
fDate
20-25 Oct 1996
Firstpage
558
Lastpage
564
Abstract
The partial scan approach is now widely adopted and several commercial tools support this technique. However, there is no general agreement on how to select the scan flip flops, in general each technique is tailored to a particular ATPG algorithm and results effective when coupled with the right ATPG tool. In this paper, we propose an approach suitable for GA-based ATPGs, which is barred on exploiting some information coming from the ATPG itself we compare the results of our method with the ones of the approach based on cutting the topological loops and use a GA-based ATPG to demonstrate its effectiveness in terms of fault coverage and CPU time
Keywords
automatic testing; computational complexity; controllability; flip-flops; logic testing; observability; sequential circuits; ATPG algorithm; CPU time; GATTO; controllability; effectiveness; fault coverage; observability; partial scan flip flop selection; sequential ATPG; Algorithm design and analysis; Automatic test pattern generation; Automatic testing; Central Processing Unit; Circuit analysis; Circuit faults; Circuit testing; Feedback loop; Sequential circuits; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 1996. Proceedings., International
Conference_Location
Washington, DC
ISSN
1089-3539
Print_ISBN
0-7803-3541-4
Type
conf
DOI
10.1109/TEST.1996.557088
Filename
557088
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