Title :
A Low Complexity VLSI Architecture for Reed-Solomon Decoder
Author :
Khalesi, Hasan ; Nabavi, A. ; Bornoosh, B.
Author_Institution :
Dept. of Electr. & Comput. Eng., Tarbiat Modares Univ., Tehran, Iran
Abstract :
Reed-Solomon (RS) codes have been widely used in a variety of communication systems to protect digital data against errors or to reduce the signal to noise ratio requirement in transmission process. This paper presents an area-efficient 8-error correcting RS (255,239) decoder architecture using RiBM algorithm, implemented on a 0.25-¿m CMOS technology with a supply voltage of 2.75 V. The total number of gates is about 12,600, which illustrates about an order of magnitude reduction compared to existing RS decoders. This improvement in hardware complexity is due to using a low complexity multiplier over GF (28) and constant multipliers. The decoder has a data processing rate of 1.6 Gbits/s at a clock frequency of 200 MHz.
Keywords :
CMOS integrated circuits; Reed-Solomon codes; VLSI; circuit complexity; decoding; error correction codes; integrated circuit design; multiplying circuits; CMOS technology; RS codes; Reed-Solomon decoder; RiBM algorithm; area-efficient 8-error correcting RS decoder architecture; bit rate 1.6 Gbit/s; communication systems; data processing rate; digital data error protection; frequency 200 MHz; hardware complexity improvement; low complexity VLSI architecture; multipliers; reformulation inversion-less Berlekamp-Massey algorithms; signal to noise ratio reduction; size 0.25 mum; voltage 2.75 V; CMOS technology; Clocks; Data processing; Decoding; Hardware; Protection; Reed-Solomon codes; Signal to noise ratio; Very large scale integration; Voltage;
Conference_Titel :
Signal Processing and Communications, 2007. ICSPC 2007. IEEE International Conference on
Conference_Location :
Dubai
Print_ISBN :
978-1-4244-1235-8
Electronic_ISBN :
978-1-4244-1236-5
DOI :
10.1109/ICSPC.2007.4728628
