Template-driven parasitic-aware optimization of analog integrated circuit layouts

Author

Bhattacharya, Sambuddha ; Jangkrajarng, Nuttorn ; Shi, C.-J.R.

Author_Institution

Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA

fYear

2005

fDate

13-17 June 2005

Firstpage

644

Lastpage

647

Abstract

Layout parasitics have great impact on analog circuit performance. This paper presents an algorithm for explicit parasitic control during layout retargeting of analog integrated circuits. In order to ensure desired circuit performance, bounds on layout parasitics´ magnitudes are determined first. Then, graph techniques are coupled with mathematical programming to constrain layout geometry based on these parasitic bounds. The algorithm has been demonstrated to ensure desired circuit performance during technology migration and performance specification changes.

Keywords

analogue integrated circuits; circuit CAD; circuit optimisation; graph theory; integrated circuit layout; analog integrated circuit layouts; analog layout automation; constrain layout geometry; graph techniques; layout parasitics; layout retargeting; mathematical programming; parasitic bounds; parasitic control; sensitivity; template-driven parasitic-aware optimization; Analog circuits; Analog integrated circuits; Automation; Circuit optimization; Computer applications; Coupling circuits; Data mining; Integrated circuit layout; Parasitic capacitance; Permission;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2005. Proceedings. 42nd

Print_ISBN

1-59593-058-2

Type

conf

DOI

10.1109/DAC.2005.193890

Filename

1510410