Coping with re-usability using sequential ATPG: a practical case study

To be able to manage increasing chip complexity, the re-use of already designed functional modules has become a standard design practise in state-of-the-art ASIC design. In this paper, the impact of these re-used modules on the testability of the entire chip has been investigated. For this purpose, a complex telecom ASIC with re-used interface logic running at 155 MHz, used in an ATM (Asynchronous Transfer Mode) application, has been studied. The single stuck-at fault coverage for the random logic, obtained with combinational ATPG, has been increased by 21% by performing some minor design modifications and using sequential ATPG. In addition, it has been shown that with respect to I_DDQ testing, automatic test vector generation has to be preferred over fault grading hand-written functional test vector sets. With I_DDQ test vector generation 95% fault coverage has been obtained with only 66% of the flip-flops being scannable