DocumentCode :
2049632
Title :
Streamline verification process with formal property verification to meet highly compressed design cycle
Author :
Chatterjee, Prosenjit
Author_Institution :
NVIDIA Corp., USA
fYear :
2005
fDate :
13-17 June 2005
Firstpage :
674
Lastpage :
677
Abstract :
In this paper, the author describes a methodology and tool flow for using formal verification effectively to reduce the verification burden in large custom ASIC designs.
Keywords :
application specific integrated circuits; formal verification; integrated circuit design; ASIC design; formal verification; Application specific integrated circuits; Computer bugs; Fault tolerance; Fluid flow measurement; Formal verification; Graphics; Permission; Processor scheduling; Production; Testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 2005. Proceedings. 42nd
Print_ISBN :
1-59593-058-2
Type :
conf
DOI :
10.1109/DAC.2005.193897
Filename :
1510417
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=2049632
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