DocumentCode
2049795
Title
Multi-bit upsets in 65nm SOI SRAMs
Author
Cannon, Ethan H. ; Gordon, Michael S. ; Heidel, David F. ; KleinOsowski, AJ ; Oldiges, Phil ; Rodbell, Kenneth P. ; Tang, Henry H K
Author_Institution
IBM Syst. & Technol. Group, Essex Junction, VT
fYear
2008
fDate
April 27 2008-May 1 2008
Firstpage
195
Lastpage
201
Abstract
We study multi-bit upsets (MBU) in 65 nm SOI SRAMs. Proton beam and thorium foil experiments demonstrate that SOI SRAMs have lower soft error rate than bulk SRAMs. Monte Carlo SER simulations show that SOI SRAMs have a lower fraction of MBU than bulk SRAMs. The probability of MBU correlates with the spacing of sensitive devices in neighboring cells.
Keywords
Monte Carlo methods; SRAM chips; error analysis; proton effects; silicon-on-insulator; Monte Carlo simulations; SOI SRAMs; multi-bit upsets; proton beam; sensitive device spacing; soft error rate; thorium foil; Alpha particles; CMOS technology; Circuits; Contacts; Error analysis; Error correction codes; Laboratories; MOSFETs; Particle beams; Random access memory; (SEU); cosmic rays; multi-bit upset; single-event upset; soft error rate (SER);
fLanguage
English
Publisher
ieee
Conference_Titel
Reliability Physics Symposium, 2008. IRPS 2008. IEEE International
Conference_Location
Phoenix, AZ
Print_ISBN
978-1-4244-2049-0
Electronic_ISBN
978-1-4244-2050-6
Type
conf
DOI
10.1109/RELPHY.2008.4558885
Filename
4558885
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