Title :
A Soc bus architecture for detecting and thwarting Ic functional viruses with reduced activation time
Author :
Gowri, D. ; Mohammed Abbas, A.
Author_Institution :
Veltech Multitech Dr. Rangarajan Dr. Sakunthala Eng. Coll., Chennai, India
Abstract :
While the issue of Trojan ICs has been receiving increasing amounts of attention, the overwhelming majority of anti-Trojan measures aim to address the problem during verification. While such methods are an important part of an overall anti-Trojan strategy, it is statistically inevitable that some Trojans will escape verification-stage detection, in particular in light of the increasing size and complexity of system-on-chip (SOC) solutions and the increasing use of third-party designs. In contrast with much of the previous work in this area, we specifically focus on run-time methods to identify the attacks of a Trojan and to adapt the system and respond accordingly. We describe a solution including a bus architecture in which the arbitration, address decoding, multiplexing, wrapping, and other components protect against malicious use of the bus.
Keywords :
circuit complexity; cryptography; integrated circuit design; integrated circuit reliability; multiplexing; system buses; system-on-chip; IC functional virus detection; SOC complexity; SOC size; SoC bus architecture; Trojan IC; activation time reduction; address decoding; antiTrojan measures; antiTrojan strategy; attack identification; malicious attack protection; multiplexing; run-time methods; system-on-chip solutions; third-party designs; verification-stage detection; wrapping; Authentication; Decoding; Flip-flops; Hardware; System-on-chip; Trojan horses;
Conference_Titel :
Information Communication and Embedded Systems (ICICES), 2013 International Conference on
Conference_Location :
Chennai
Print_ISBN :
978-1-4673-5786-9
DOI :
10.1109/ICICES.2013.6508174