• DocumentCode
    2049894
  • Title

    Beyond safety: customized SAT-based model checking

  • Author

    Ganai, Malay K. ; Gupta, Aarti ; Ashar, Pranav

  • fYear
    2005
  • fDate
    13-17 June 2005
  • Firstpage
    738
  • Lastpage
    743
  • Abstract
    Model checking of safety properties has taken a significant lead over nonsafety properties in recent years. To bridge the gap, we propose dedicated SAT-based model checking algorithms for properties beyond safety. Previous bounded model checking (BMC) approaches have relied on either converting such properties to safety checking, or finding proofs by deriving termination criteria using loop-free path analysis. Instead, our approach uses a customized SAT-based formulation for bounded model checking of nonsafety properties, and determines the completeness bounds for liveness using unbounded SAT-based analysis. Our main contributions are: 1) Customized property translations for LTL formulas for BMC, with novel features that utilize partitioning, learning, and incremental formulation. Customized translations not only improve the BMC performance significantly in comparison to standard monolithic LTL translations, but also allow efficient derivation and use of completeness bounds. Though we discuss the translation schemas for liveness, they can be easily extended to handle other LTL properties as well. 2) Customized formulations for determining completeness bounds for liveness using SAT-based unbounded model checking (UMC) rather than using loop-free path analysis. These formulations comprise greatest fixed-point and least fixed-point computations to efficiently handle nested properties using SAT-based quantification approaches. We show the effectiveness of our overall approach for checking liveness on public benchmarks and several industry designs.
  • Keywords
    circuit CAD; formal verification; BMC performance; LTL formulas; LTL properties; SAT-based model checking; SAT-based quantification; bounded model checking; circuit cofactoring; completeness bounds; customized SAT-based formulation; customized formulations; customized model checking; customized property translations; formal verification; greatest fixed-point computations; incremental formulation; industry designs; learning; least fixed-point computations; liveness translation schemas; loop-free path analysis; model checking algorithms; monolithic LTL translations; nested properties handling; nonsafety properties; public benchmarks; safety checking; safety properties; termination criteria derivation; unbounded SAT-based analysis; unbounded model checking; Algorithm design and analysis; Bridge circuits; Data structures; Educational institutions; Formal verification; Induction generators; Laboratories; National electric code; Permission; Safety;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 2005. Proceedings. 42nd
  • Print_ISBN
    1-59593-058-2
  • Type

    conf

  • DOI
    10.1109/DAC.2005.193909
  • Filename
    1510429