DocumentCode :
2050076
Title :
Low-complexity fault simulation under the multiple observation time testing approach
Author :
Pomeranz, Irith ; Reddy, Sudhakar M.
Author_Institution :
Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
fYear :
1995
fDate :
21-25 Oct 1995
Firstpage :
272
Lastpage :
281
Abstract :
The use of three-value logic for fault simulation of synchronous sequential circuits may incur a loss of accuracy that would cause the fault coverage to be underestimated. In addition, loss of fault coverage may occur due to the test strategy employed. These problems were previously alleviated at the cost of high computational complexity. We present an observation that allows us to alleviate loss of fault coverage in many cases, at a computational cost similar to conventional three-value fault simulation. The proposed simulation procedure is compared to a previously proposed one to demonstrate its effectiveness
Keywords :
automatic test software; circuit analysis computing; computational complexity; design for testability; fault diagnosis; logic CAD; logic testing; sequential circuits; ternary logic; ATPG; DFT; computational cost; logic testing; loss of fault coverage; low-complexity fault simulation; multiple observation time testing approach; random patterns; synchronous sequential circuits; three-value implication procedure; three-value logic; Circuit faults; Circuit simulation; Circuit testing; Cities and towns; Computational efficiency; Computational modeling; Fault detection; Logic testing; Sequential analysis; Sequential circuits;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Conference, 1995. Proceedings., International
Conference_Location :
Washington, DC
ISSN :
1089-3539
Print_ISBN :
0-7803-2992-9
Type :
conf
DOI :
10.1109/TEST.1995.529842
Filename :
529842
Link To Document :
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