Title :
Modeling of majority and minority carrier triggered external latchup
Author :
Farbiz, Farzan ; Rosenbaum, Elyse
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Illinois at Urbana-Champaign, Urbana, IL
fDate :
April 27 2008-May 1 2008
Abstract :
Circuit models are presented that allow one to identify the worst-case testing condition for external latchup and to simulate the value of the latchup trigger current. The models are valid under both moderate and high-level injection. A good fit between the model and the measurements is observed. The roles of substrate majority and minority carriers are elucidated.
Keywords :
CMOS logic circuits; flip-flops; integrated circuit design; integrated circuit modelling; logic design; logic testing; CMOS latchup; circuit models; external latchup testing; high-level carrier injection; latchup trigger current; substrate majority carriers; substrate minority carriers; Circuit simulation; Circuit testing; Computational modeling; Computer simulation; Diodes; Rails; Standards development; Stress; Switching circuits; Voltage control; Circuit models; Latchup;
Conference_Titel :
Reliability Physics Symposium, 2008. IRPS 2008. IEEE International
Conference_Location :
Phoenix, AZ
Print_ISBN :
978-1-4244-2049-0
Electronic_ISBN :
978-1-4244-2050-6
DOI :
10.1109/RELPHY.2008.4558897
