FPGA based high speed design for blind equalization of 8PSK signals

A high speed structure for blind equalization of 8PSK signals is presented based on FPGA. The filter section is designed with a parallel structure based on time-domain convolution. In the case of short delay spread, this structure is superior to the parallel structure based on sub-convolution filter bank in literature on computational complexity. Applying this structure to the blind equalization of 800Mbps 8PSK signals, test results show that the speed requirement is met, the hardware resources are furthest saved, and the blind equalizer converges fast.