Author :
Pae, S. ; Agostinelli, M. ; Brazier, M. ; Chau, R. ; Dewey, G. ; Ghani, T. ; Hattendorf, M. ; Hicks, J. ; Kavalieros, J. ; Kuhn, K. ; Kuhn, M. ; Maiz, J. ; Metz, M. ; Mistry, K. ; Prasad, C. ; Ramey, S. ; Roskowski, A. ; Sandford, J. ; Thomas, C. ; Thomas
Abstract :
In this paper, bias-temperature instability (BTI) characterization on 45nm high-K + metal-gate (HK+MG) transistors is presented and degradation mechanism is discussed. Transistors with an unoptimized HK film stack in the early development phase exhibited pre-existing traps and large amount of hysteresis that was consistent with literature. The optimized and final HK process demonstrated NMOS and PMOS BTI on HK+MG transistors that are better than that of SiON at matched E-fields and comparable at targeted 30% higher use fields. The final process also showed no hysteresis due to fast traps thereby allowing us to characterize its intrinsic degradation mechanism. On the optimized process, NMOS BTI is attributed primarily to electron trapping in the HK bulk and HK/SiON interfacial layer (IL) regions. PMOS BTI degradation, on the other hand, is mainly interface driven and is found to be very similar to that observed on conventional SiON transistors.
Keywords :
MOSFET; high-k dielectric thin films; semiconductor device reliability; semiconductor technology; BTI reliability; NMOS transistors; PMOS transistors; bias-temperature instability; electron trapping; high-K + metal-gate process technology; interfacial layer regions; intrinsic degradation mechanism; size 45 nm; Electrodes; Electron traps; Gate leakage; High K dielectric materials; High-K gate dielectrics; Hysteresis; Leakage current; Logic; MOS devices; Thermal degradation; BTI; High-K; Metal gate; Reliability; Transistors;
