A designer´s view of chip test

Author

Anderson, Thomas L.

Author_Institution

Adv. Micro Devices Inc., Sunnyvale, CA, USA

fYear

1995

fDate

21-25 Oct 1995

Firstpage

292

Abstract

Attempts to link design and test are discussed. They are shown to have some value and all have been employed successfully by many engineers in both domains. A “wish list” is presented which summarizes some ways to make this process easier: (1) Test engineers need to be involved in simulation. (2) ATPG tools must evolve to support path delay testing and other techniques that leverage static timing analysis. (3) More effective use should be made of BIST approaches. (4) Finally, it would be nice if testers always had enough memory so that test engineers didn´t have to deal with RTZ signals and the like. A more direct mapping from simulation to the tester would be the result

Keywords

automatic testing; built-in self test; circuit analysis computing; design for testability; fault diagnosis; integrated circuit testing; logic CAD; logic testing; timing; ATPG tools; BIST; HDL; chip test; logic design; logic testing; path delay testing; simulation; static timing analysis; virtual testbench; Automatic test pattern generation; Automatic testing; Built-in self-test; Design engineering; Electronic design automation and methodology; Logic testing; Manufacturing industries; Test pattern generators; Timing; Virtual manufacturing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1995. Proceedings., International

Conference_Location

Washington, DC

ISSN

1089-3539

Print_ISBN

0-7803-2992-9

Type

conf

DOI

10.1109/TEST.1995.529844

Filename

529844