Advantages of high level test synthesis over design for test

There are two major reasons why high-level test synthesis (HLTS) has advantages over design for testability (DFT) at low level: (l) size complexity and (2) functional abstraction. A design grows significantly in size when it is synthesized into a low level description. For example, the behavioral description of an FIR filter in Silage language required only one page, whereas the structural VHDL of the same design at gate level required as much as forty pages. This explosion in size complexity causes a loss in the effectiveness of any automated tool. The second advantage, functional abstraction, allows one to utilize specific functional behaviors, that can be used for various activities during ATPG. For example, it is easy to identify that an adder will propagate a pattern at one of the inputs to its output provided the other input is zero, but at the gate level it requires a large amount of search to derive the same information. HLTS has access to more information than low-level DFT, hence the former is capable of achieving more than the latter. As we go higher in the description, the more functional abstraction we can get, thereby making the testing tasks easier