Mitigation techniques for single event induced charge sharing in a 90 nm bulk CMOS process

Author

Amusan, O.A. ; Massengill, L.W. ; Baze, M.P. ; Bhuva, B.L. ; Witulski, A.F. ; Black, J.D. ; Balasubramanian, A. ; Casey, M.C. ; Black, D.A. ; Ahlbin, J.R. ; Reed, R.A. ; McCurdy, M.W.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Vanderbilt Univ., Nashville, TN

fYear

2008

fDate

April 27 2008-May 1 2008

Firstpage

468

Lastpage

472

Abstract

Mitigation techniques to reduce the increased SEU cross-section associated with charge sharing in a 90 nm DICE latch are proposed. The increased error cross-section is caused by heavy ion angular strikes depending on the directionality of the ion vector, thereby exacerbating charge sharing among multiple circuit nodes. The use of nodal separation as a mitigation technique shows an order of magnitude decrease on upset cross-section compared to a conventional layout and the use of guard-rings show no noticeable effect on upset cross-section.

Keywords

CMOS integrated circuits; error analysis; flip-flops; integrated circuit design; ion beam effects; radiation hardening; bulk CMOS process; dual interlocked cell latch; guard-rings; heavy ion angular strikes; ion vector; mitigation techniques; multiple circuit nodes; nodal separation; radiation-hardened-by-design latch array; single event induced charge sharing; size 90 nm; soft error cross-section; CMOS process; Circuit synthesis; Isolation technology; Latches; MOS devices; MOSFETs; Rails; Redundancy; Single event upset; Space charge; Dual Interlocked Cell (DICE) latch; charge sharing; guard-rings; heavy-ion; nodal separation; single event circuit characterization; soft error cross-section;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium, 2008. IRPS 2008. IEEE International

Conference_Location

Phoenix, AZ

Print_ISBN

978-1-4244-2049-0

Electronic_ISBN

978-1-4244-2050-6

Type

conf

DOI

10.1109/RELPHY.2008.4558930

Filename

4558930