DocumentCode
2051373
Title
Design and performances of a compensated mean timer
Author
Dzahini, D. ; Pouxe, J. ; Rosetto, O.
Author_Institution
Inst. des Sci. Nucl., Univ. Joseph Fourier, Grenoble, France
Volume
2
fYear
1999
fDate
1999
Firstpage
744
Abstract
An integrated mean timer has been designed. This circuit integrates a compensation system in order to minimize thermal drift and process variations. This circuit designed in BiCMOS 0.8 μm integrates input and output ECL translators. The drift cancellation system is based on a regulated delay line controlled by a PLL. The PLL circuit can be disconnected and an external control voltage can be used. The circuit can also run without any cancellation system. In the last part, a sub-delay resolution system is discussed
Keywords
CMOS digital integrated circuits; digital phase locked loops; nuclear electronics; timing circuits; compensated mean timer; compensation system; drift cancellation system; external control voltage; process variations; regulated delay line; sub-delay resolution system; thermal drift; BiCMOS integrated circuits; Capacitors; Control systems; Delay lines; Detectors; Inverters; Phase locked loops; Photomultipliers; Physics; Voltage control;
fLanguage
English
Publisher
ieee
Conference_Titel
Nuclear Science Symposium, 1999. Conference Record. 1999 IEEE
Conference_Location
Seattle, WA
ISSN
1082-3654
Print_ISBN
0-7803-5696-9
Type
conf
DOI
10.1109/NSSMIC.1999.845775
Filename
845775
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