Design of high speed low power viterbi decoder for TCM system

Viterbi decoder is the most power hungry module in the Trelli coded modulation system. In VLSI implementation, reduced chip area, low power consumption, improved speed are the main concerns to be obtained. In this brief, high speed low power Viterbi algorithm architecture is proposed to decode the high rate convolution codes. Constraint length of high rate convolution code should be high to maintain low error probability. But computational complexity of the Viterbi algorithm for high rate convolution code increases exponentially with the constraint length. This computational problem can be solved by trimming the least likely paths at each trelli stage in the T-algorithm; as a result significant power reduction can also be achieved. Furthermore, the pre-computation technique is used to speed up the process of searching for the optimal path metric from the ACSU loop. Architecture of the Add-Compare-Select loop is modified using the pre-computation architecture. This shortens the long critical path introduced by the conventional T-algorithm. Register exchange algorithm is used for the survivor memory unit design, since it is faster and requires lesser memory. Conceptually, Register exchange algorithm has a pre-defined end state. Since the optimized T-algorithm is used, pre-defining the end state is not possible. This issue is focused and appropriate solution is provided in this paper. From the simulation results it is observed that the proposed Viterbi decoder architecture can reduce significant amount of computations, power consumption with negligible performance reduction.