• DocumentCode
    2051594
  • Title

    Mechanism of snapback failure induced by the latch-up test in high-voltage CMOS integrated circuits

  • Author

    Tseng, Jen-Chou ; Chen, Yu-Lin ; Hsu, Chung-Ti ; Tsai, Fu-Yi ; Chen, Po-An ; Ker, Ming-Dou

  • Author_Institution
    Device Technol. Dev. Div., Winbond Electron. Corp., Hsinchu
  • fYear
    2008
  • fDate
    April 27 2008-May 1 2008
  • Firstpage
    625
  • Lastpage
    626
  • Abstract
    An electrical overstress failure induced by a latch-up test is studied in high-voltage integrated cricuits. The latchup test resulted in damage to the output NMOSFET due to snapbach and also resulted in a latch-up in the internal circuits. These mechanisms are analyzed and solutions are proposed to avoid the triggering of the output NMOSFET and the resulting latchup issue.
  • Keywords
    CMOS integrated circuits; flip-flops; NMOSFET; electrical overstress failure; high-voltage CMOS integrated circuits; high-voltage integrated cricuits; latch-up test; snapback failure; CMOS integrated circuits; Circuit testing; Integrated circuit interconnections; Integrated circuit testing; MOSFET circuits; Pulse width modulation; Regulators; Substrate hot electron injection; Thyristors; Voltage; EOS; ESD; high-voltage; latch-up;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Reliability Physics Symposium, 2008. IRPS 2008. IEEE International
  • Conference_Location
    Phoenix, AZ
  • Print_ISBN
    978-1-4244-2049-0
  • Electronic_ISBN
    978-1-4244-2050-6
  • Type

    conf

  • DOI
    10.1109/RELPHY.2008.4558958
  • Filename
    4558958
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2051594