DocumentCode :
2051825
Title :
[Title pages]
fYear :
2013
fDate :
2-4 Oct. 2013
Firstpage :
1
Lastpage :
14
Abstract :
In today\´s world there is an explosive growth in digital information content. Moreover, there is also a rapid increase in the number of users of multimedia applications related to image and video processing, recognition, mining and synthesis. These facts pose an interesting design challenge to process digital data in an energy-efficient manner while catering to desired user quality requirements. Most of these multimedia applications possess an inherent quality of "error"-resilience. This means that there is considerable room for allowing approximations in intermediate computations, as long as the final output meets the user quality requirements. This relaxation in "accuracy" can be used to simplify the complexity of computations at different levels of design abstraction, which directly helps in reducing the power consumption. At the algorithm and architecture levels, the computations can be divided into significant and non-significant. Significant computations have a greater impact on the overall output quality, compared to non-significant ones. Thus the underlying architecture can be modified to promote faster computation of significant components, thereby enabling voltage-scaling (at the same operating frequency). At the logic and circuit levels, one can relax Boolean equivalence to reduce the number of transistors and decrease the overall switched capacitance. This can be done in a controlled manner to introduce limited approximations in common mathematical operations like addition and multiplication. All these techniques can be classified under the general topic of "ApproximateComputing", which is the main focus of this talk.
Keywords :
VLSI; approximation theory; fault tolerance; integrated circuit design; logic circuits; nanotechnology; Boolean equivalence; DFTS; VLSI; addition; approximate computing; circuit level; defect; design challenge; digital data processing; digital information content; error-resilience; fault tolerance; image processing; logic level; mathematical operations; mining; multimedia applications; multiplication; nanotechnology systems; power consumption reduction; recognition; switched capacitance; synthesis; transistors; user quality requirements; video processing; voltage-scaling; Abstracts; Switches; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2013 IEEE International Symposium on
Conference_Location :
New York City, NY
ISSN :
1550-5774
Print_ISBN :
978-1-4799-1583-5
Type :
conf
DOI :
10.1109/DFT.2013.6653573
Filename :
6653573
Link To Document :
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