Efficient memory optimization and high throughput decoding architecture based on LDPC codes

Low-Density Parity-Check (LDPC) code is one kind of prominent error correcting codes (ECC) being considered in next generation industry standards. Here, the memory bandwidth is the key performance limiting factor. And the decoding throughput of a LDPC decoder is limited by this memory bandwidth requirement. The decoder implementation complexity has been the bottleneck of its application. This paper present a specific optimization called vectorization to take advantage of the configurable data-width and depth of embedded memory in an FPGA to improve the throughput of a decoder for quasicyclic LDPC codes. It is shown that this presented hardware structure will be highly competent in high throughput and low decoding latency applications.