Test quality: required stuck-at fault coverage with the use of I DDQ testing

Users of integrated circuits requiring very high quality are forced to generate specifications that contain quality metrics that are universally understood and applied by all the suppliers of integrated circuits. Stuck-at fault coverage has been classically used as such a metric. However, innumerable reports question the validity of the SAF model as the best metric for insuring CMOS circuit quality. Papers from each of the last four ITC´s have detailed the fallacy of relying solely on high SAF coverage. Several other fault models (delay, bridging, weak0/1, pseudo stuck-at, etc.) have been introduced and their results evaluated. The conclusion seems to be that each method adds some amount to the total test coverage, while no method by itself is sufficient. The optimum test strategy should contain several types of tests targeted to the failure and defect mechanisms that apply to the circuit design and manufacturing technology in question. The problem here, especially from the user perspective, is that defining a `universal´ quality metric becomes very difficult or impossible. The AEC has proposed, in our most recent Fault Simulation and Test Grading specification (AEC-Q100-007), that the inclusion of an I_DDQ test in the test flow is desired and that the resulting improvement in total fault coverage is sufficient to allow the use of a test program with SAF coverage >95% in production. Overall test coverage and incoming product quality is expected to improve