Title :
A fast TCAD-based methodology for Variation analysis of emerging nano-devices
Author :
Mohammadi, Hassan Ghasemzadeh ; Gaillardon, Pierre-Emmanuel ; Yazdani, Mojtaba ; De Micheli, G.
Author_Institution :
Integrated Syst. Lab., EPFL, Lausanne, Switzerland
Abstract :
Variability analysis of nanoscale transistors and circuits is emerging as a necessity at advanced technology nodes. Technology Computer Aided Design (TCAD) tools are powerful ways to get an accurate insight of Process Variations (PV). However, obtaining both fast and accurate device simulations is impractical with current TCAD solvers. In this paper, we propose an automated output prediction method suited for fast PV analysis. Coupled with TCAD simulations, our methodology can substantially reduce the time complexity and cost of variation analysis for emerging technologies. We overcome the simulation obstacles and preserve accuracy, using a neural network based regression to predict the output of individual process simulations. Experiments indicate that, after the training process, the proposed methodology effectively accelerate TCAD-based PV simulations close to compact-model-based simulations. Therefore, the methodology can be an excellent opportunity in enabling extensive statistical simulations such as Monte-Carlo for emerging nano-devices.
Keywords :
Monte Carlo methods; circuit complexity; circuit simulation; electronic engineering computing; nanoelectronics; neural nets; regression analysis; technology CAD (electronics); Monte-Carlo; PV simulations; TCAD simulations; automated output prediction method; compact-model-based simulations; device simulations; individual process simulations; nanodevices; nanoscale transistors; neural network based regression; process variations; simulation obstacles; statistical simulations; technology computer aided design tools; time complexity; training process; variation analysis; Analytical models; Computational modeling; Data models; Integrated circuit modeling; Mathematical model; Predictive models; Training;
Conference_Titel :
Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2013 IEEE International Symposium on
Conference_Location :
New York City, NY
Print_ISBN :
978-1-4799-1583-5
DOI :
10.1109/DFT.2013.6653587