FPGA based front-end electronics for a high resolution PET scanner

A high resolution PET scanner requiring processing electronics for 936 block technology channels and just under sixty-thousand crystal elements has been developed. With the advances in flexibility, number of gates, lower costs and speed of FPGAs, an FPGA implementation of the front-end processing electronics was chosen over the traditional discrete logic or ASIC. The FPGA architecture reduced the development time and risks compared to a mask-based ASIC architecture while keeping costs and electronics packing density comparable. The extensive use FPGAs enables much faster circuit realization and a very efficient logic utilization by allowing reconfiguration of the electronics functionality to support system setup, self-diagnostics, and several calibration modes for detector setup. Logic realized within the FPGAs performs the crystal selection, energy qualification, time correction, depth of interaction determination, and event counting functions. Since the FPGAs are in-circuit reconfigurable, the functionality of the electronics is easily modified to support the different modes of operation. Thus the development time is reduced as well as the amount of electronics required, saving board area, power consumption and costs