Title :
Characterization of stress-voiding of Cu / Low-k vias attached to narrow lines
Author :
Lin, H.Y. ; Lee, S.C. ; Oates, A.S.
Author_Institution :
TSMC9, Hsinchu
fDate :
April 27 2008-May 1 2008
Abstract :
We show that the mechanism of stress voiding in Cu/low-k vias is independent of width in the range 0.07 - 0.42 squarem. The resistance change associated with voiding shows saturation with stress time, implying that stress voiding is not a fundamental concern for continued feature size scaling. Stress voiding at narrow w is very sensitive to interconnect processing, and can give unexpected, large resistance increases with annealing.
Keywords :
annealing; copper; integrated circuit interconnections; Cu; annealing; feature size scaling; interconnect processing; stress voiding; Annealing; Dielectrics; Electrical resistance measurement; Failure analysis; Geometry; Kinetic theory; Predictive models; Stress measurement; Testing; Time measurement;
Conference_Titel :
Reliability Physics Symposium, 2008. IRPS 2008. IEEE International
Conference_Location :
Phoenix, AZ
Print_ISBN :
978-1-4244-2049-0
Electronic_ISBN :
978-1-4244-2050-6
DOI :
10.1109/RELPHY.2008.4558989
