Title :
A hierarchical, design-for-testability (DFT) methodology for the rapid prototyping of application-specific signal processors (RASSP)
Author :
Sedmak, Richard ; Evans, John
Author_Institution :
Lockheed Martin Adv. Technol. Labs., USA
Abstract :
This paper describes a highly automated hierarchical, design-for-testability process that spans the entire life cycle. Lockheed Martin´s Advanced Technology Laboratories and Self-Test Services developed this process for the DoD´s RASSP program, and it contributes significantly to the RASSP goals of 4× improvement in cycle time, design quality, and life-cycle costs
Keywords :
application specific integrated circuits; built-in self test; circuit CAD; computer architecture; design for testability; digital signal processing chips; hierarchical systems; integrated circuit design; military equipment; production testing; software prototyping; BIST; DFT; DoD; Lockheed Martin´s Advanced Technology Laboratories; RASSP program; Self-Test Services; application-specific signal processors; cycle time; design quality; hierarchical design-for-testability; life-cycle costs; rapid prototyping; signal processors; Automatic testing; Circuit testing; Costs; Design for testability; Design methodology; Life testing; Prototypes; Signal design; Signal processing; System testing;
Conference_Titel :
Test Conference, 1995. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-2992-9
DOI :
10.1109/TEST.1995.529856
