F-DICE: A multiple node upset tolerant flip-flop for highly radioactive environments

Author

Campitelli, Stefano ; Ottavi, Marco ; Pontarelli, Salvatore ; Marchioro, A. ; Felici, Daniele ; Lombardi, Floriana

Author_Institution

Electron. Eng. Dept., Univ. of Rome Tor Vergata, Rome, Italy

fYear

2013

fDate

2-4 Oct. 2013

Firstpage

107

Lastpage

111

Abstract

This paper introduces a novel design for a multiple node upset tolerant flip-flop. This design uses the TDICE memory cell that was proposed in the technical literature for memory arrays and applies its principles of operation to a Master Slave flip-flop implemented at 65 nm CMOS technology. It is shown that the proposed design approach is particularly suited for flip-flops targeting highly radioactive environments; simulation validates the multiple node upset tolerance and its viability. A test chip developed for the on-silicon validation is also described.

Keywords

CMOS logic circuits; flip-flops; logic design; memory architecture; radiation effects; CMOS technology; F-DICE; TDICE memory cell; master slave flip-flop; memory arrays; multiple node upset tolerance; multiple node upset tolerant flip-flop; on-silicon validation; radioactive environments; technical literature; Clocks; Fault tolerance; Fault tolerant systems; Latches; Single event upsets; Transistors; Very large scale integration; Flip flop; Multiple node upset; radiation;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2013 IEEE International Symposium on

Conference_Location

New York City, NY

ISSN

1550-5774

Print_ISBN

978-1-4799-1583-5

Type

conf

DOI

10.1109/DFT.2013.6653591

Filename

6653591