A study of SONOS charge loss mechanism after hot-hole stressing using trap-layer engineering and electrical re-fill methods

The high-Vt state data retention of 2bit/cell SONOS using hot-hole erasing method is studied extensively using a 0.13 mum virtual-ground array NOR-type test chip. We design various trap-layer engineering using multi-layer stacks of SiN and SiON in order to change the intra-nitride conduction. However, our results show that the post-cycled retention is insensitive to the trap-layer engineering. Next, we apply the electrical refill method to test the retention, and find that retention can be improved. Hence our results supports the trap assisted charge loss mechanism. Finally, using a novel bit-by-bit tracking technique, we find that the retention behavior of an individual bit has a random but wide distribution, and some tail bits even show abnormal charge gain. This suggests that both electron and hole de-trapping happen during retention.