DocumentCode :
2052426
Title :
Generic software framework for a line -buffer based GPU (reconstruction pipeline)
Author :
Kalingarani, G. ; Karthikeyan, S.
Author_Institution :
Dept. of CSE, Arunai Eng. Coll., Thiruvannamalai, India
fYear :
2013
fDate :
21-22 Feb. 2013
Firstpage :
866
Lastpage :
871
Abstract :
As the graphical capabilities of personal computers have increased, hardware manufacturers discovered that there were advantages to creating specialized hardware to perform mathematical operations commonly used in graphics rendering. This eventually resulted in the advent of modern video cards with Graphics Processing Units as their core processing units. Graphics Processing Unit utilize a highly parallel architecture composed of many more but smaller processing elements capable of a high degree of data level parallelism. Graphics Processing Unit are very much designed to be SIMD. This was originally for the purpose of accessing multiple pixels simultaneously to improve computer graphics performance. This paper presents a generic software framework for a line - buffer based image reconstruction pipeline. The presented framework is capable of operating in low-memory environments and significantly eases algorithm insertions, changes of processing order, and other pipeline management tasks. The savings in development time can be even months. In addition, our experiments show that it offers over 99% memory savings compared with traditional implementations using a matrix-matrix Multiplication for construction with ping-pong buffer scheme full-sized image buffers. The implemented framework also enhances processing performance due to better cache usage and increases flexibility with various pipeline configurations.
Keywords :
cache storage; graphics processing units; image reconstruction; matrix multiplication; parallel architectures; parallel processing; pipeline processing; rendering (computer graphics); SIMD; cache usage; data level parallelism; full-sized image buffers; generic software framework; graphics processing units; graphics rendering; hardware manufacturers; image reconstruction pipeline; line-buffer based GPU; low-memory environments; mathematical operations; matrix-matrix Multiplication; parallel architecture; personal computers; ping-pong buffer scheme; pipeline configurations; pipeline management tasks; video cards; Cameras; Face; Graphics processing units; Image edge detection; Image reconstruction; Pipelines; Streaming media; Least significant bit (LSB); adaptive pixel pair matching (APPM); diamond encoding (DE); exploiting modification direction (EMD); optimal pixel adjustment process (OPAP); pixel pair matching (PPM);
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Information Communication and Embedded Systems (ICICES), 2013 International Conference on
Conference_Location :
Chennai
Print_ISBN :
978-1-4673-5786-9
Type :
conf
DOI :
10.1109/ICICES.2013.6508274
Filename :
6508274
Link To Document :
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