DocumentCode :
2052440
Title :
Analyzing the Performance Bottlenecks of the POWER7-IH Network
Author :
Kerbyson, Darren J. ; Barker, Kevin J.
Author_Institution :
Performance & Archit. Lab. (PAL), Pacific Northwest Nat. Lab., Richland, WA, USA
fYear :
2011
fDate :
26-30 Sept. 2011
Firstpage :
244
Lastpage :
252
Abstract :
In this work we provide an early performance analysis of the communication network in a small-scale POWER7-IH processing system from IBM. Using a set of communication micro-benchmarks we quantify the achievable bandwidth of the communication links available in the system that differ in their peak performance characteristics. We also identify the bottlenecks within the communication network and show that the bandwidth a single node can inject into the network is considerably less than the bandwidth available to the IBM hub chip, that acts as a NIC to the node as well as being an integral part of the P7-IH network. Using a communication pattern that is representative of activities in many scientific applications that have regular communication patterns, we show how the default task-to-core assignment on the P7-IH achieves sub-optimal performance in most cases. We also show that when using a diagonal-cyclic assignment, as developed in this work that takes into account the network topology as well as routing strategy, the communication performance can be improved by up to 75%. We expect even greater improvements in the communication performance on larger P7-IH systems.
Keywords :
multiprocessing systems; multiprocessor interconnection networks; network interfaces; network routing; network topology; performance evaluation; IBM hub chip; NIC; P7-IH network; POWER7-IH network; communication link; communication network; communication pattern; diagonal-cyclic assignment; network topology; performance bottleneck analysis; performance characteristics; routing strategy; small-scale POWER7-IH processing system; task-to-core assignment; Bandwidth; Communication channels; Network topology; Production; Routing; Tin; Topology; High Performance Computing; Performance Analysis; Performance Optimization; Task mapping;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Cluster Computing (CLUSTER), 2011 IEEE International Conference on
Conference_Location :
Austin, TX
Print_ISBN :
978-1-4577-1355-2
Electronic_ISBN :
978-0-7695-4516-5
Type :
conf
DOI :
10.1109/CLUSTER.2011.35
Filename :
6061142
Link To Document :
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