Title :
A novel method to analyze and design a NWL scheme DRAM
Author :
Park, Seokhan ; Sung, Bonggu ; Jung, Hyuckchai ; Lim, Junhee ; Lee, Sangwoon ; Lee, Jooyoung ; Yang, Wonsuk ; Oh, Kyungseok ; Chung, TaeYoung ; Kim, Kinam
Author_Institution :
Memory Div., Samsung Electron. Co. Ltd., Hwasung
fDate :
April 27 2008-May 1 2008
Abstract :
One of the most important issues for DRAM development is the control of data retention time. A negatively-biased off-state level of the word line (NWL) was introduced to the memory cell design to improve cell transistor "on" current and to maintain "off current sufficiently low. This paper discusses a method to design cell transistor and NWL bias level to improve the data retention time in DRAM with NWL.
Keywords :
DRAM chips; integrated circuit design; DRAM cells; data retention time; negatively-biased word line off-state level; Degradation; Doping; Failure analysis; Leakage current; Pattern matching; Probability distribution; Random access memory; Subthreshold current; Time measurement;
Conference_Titel :
Reliability Physics Symposium, 2008. IRPS 2008. IEEE International
Conference_Location :
Phoenix, AZ
Print_ISBN :
978-1-4244-2049-0
Electronic_ISBN :
978-1-4244-2050-6
DOI :
10.1109/RELPHY.2008.4558996
