Variation-tolerant cache by two-layer error control codes

In this paper, we explore a two-layer error control codes (ECC), which combines rectangular and Hamming product codes in an efficient way to address process and supply voltage variation in cache. Two-layer ECC employs simple rectangular codes for each cache line to detect error, while loading extra Hamming product codes check bits in the case of error detection; thus enabling process and supply voltage variation-tolerant cache design. Our analysis and experimental results shows that compared to complex 4-way 4EC5ED, two-layer ECC can increase Mean-Error-To-Failure by more than 2×, improve reliability by two order of magnitude under process variation, and reduce residual failure rate by one order of magnitude under supply voltage variation. Compared to simple 8-way SECDED, two-layer ECC shows a 28x-133x improvement in METF, and residual failure rate are improved furthermore.