A Partial Reconfiguration-based scheme to mitigate Multiple-Bit Upsets for FPGAs in low-cost space applications

Conventionally, the design of fault-tolerant architectures for space applications has mainly been focused on reliability and correction latency. However, based on cost reduction requirements, the power consumption must also be minimized, as it impacts the battery size and the weight of the satellite. While technology scaling helps in this purpose, it also increases the circuit sensitivity to Multiple-Bit Upsets (MBU), thus specific design techniques must be applied to compensate this effect. In order to leverage high-performance and low-cost Commercial Off-The-Shelf (COTS) FPGAs in space applications, this work tackles fault tolerance along three abstraction levels: circuit, organization and control. At the circuit level, a new ultra-low overhead Forward Temporal Redundancy (FTR) scheme is proposed for error detection in user logic. At the organization level in the FPGA, this work leverages the opportunities brought by frame- and module-based Dynamic Partial Reconfiguration (DPR) to handle configuration memory errors. At the control level, this work fully exploits the modern Xilinx Zynq System-on-Chip FPGA which embeds a hard processor used for circuit state preservation with checkpointing and rollback. The overall topology is successfully validated with 99.998% reliability through fault-injection for a five-stage pipelined MIPS processor at a global resource overhead of only 85% in LUTs and 125% in flip-flops.