Charge sharing aware NCL gates design

Interest in asynchronous circuits has increased in the VLSI research community due the growing limitations faced during the design of synchronous circuits, which often result in over constrained design and operation. For designing asynchronous circuits quasi-delay-insensitive approaches are often preferable due to their simple timing analysis and closure. Null Convention Logic (NCL) is a style that supports quasi-delay-insensitive design and enables power-, area- and speed-efficient circuits using a standard-cell methodology. However, the correct functionality of such circuits can be jeopardized by glitches caused by charge sharing effects, which can generate single event upsets. This work scrutinizes the electrical behavior of NCL gates and proposes design optimizations that improve their robustness to charge sharing glitches. Experimental results suggest that the proposed optimizations lead to more robust implementations, increasing fault avoidance and reliability in such circuits.