Reliability analysis of combinational circuits with the influences of noise and single-event transients

Author

Kaikai Liu ; Hao Cai ; Ting An ; Naviner, L. ; Naviner, Jean-Francois ; Petit, Herve

Author_Institution

Inst. Mines-TELECOM, TELECOM-ParisTech, Paris, France

fYear

2013

fDate

2-4 Oct. 2013

Firstpage

218

Lastpage

223

Abstract

Noise-immunity is an important design criterion with CMOS dimension scaling to nanometers. Furthermore, nanometer circuits devices are also more prone to soft errors induced by single event transients (SETs). In this work, we set up a model to analyze the reliability induced by both SETs and noise. We derive the constraints for the reliability enhancement of logic circuits for allowing design circuits with both better noise-immunity and higher tolerance to soft errors. Simulation combining Hspice and Matlab are given to verify the proposed constraints.

Keywords

CMOS logic circuits; SPICE; combinational circuits; integrated circuit noise; integrated circuit reliability; mathematics computing; radiation hardening (electronics); transients; CMOS dimension scaling; Hspice; Matlab; combinational circuits; logic circuits; nanometer circuits; noise immunity; reliability analysis; single-event transients; soft errors; Integrated circuit modeling; Integrated circuit reliability; Logic gates; Mathematical model; Noise; Semiconductor device modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2013 IEEE International Symposium on

Conference_Location

New York City, NY

ISSN

1550-5774

Print_ISBN

978-1-4799-1583-5

Type

conf

DOI

10.1109/DFT.2013.6653609

Filename

6653609