Envisioning self-verification of electronic systems

The verification of embedded systems remains to be a challenging task. The ever-increasing complexity as well as time-to-market constraints frequently force designers to terminate the verification process before 100% functional correctness can be ensured. This allows bugs to escape into the final product. All research activities aiming for addressing this problem rely on iterative improvements of existing solutions which remain unable to comprehensively cover the issue. In this paper, a fundamental change in how to approach the verification problem is envisioned. We propose the concept of self-verification - a methodology which enables the system itself to eventually complete all the verification tasks that could not be mastered before production. Besides the envisioned methodology, we sketch directions towards its realization and discuss possible application scenarios. By this, we provide a complementary new idea that may have the potential to overcome today´s verification crisis.