Impact of PVT variation on delay test of resistive open and resistive bridge defects

This paper presents an in-depth analysis of resistive open and resistive bridge defects behavior under process, voltage and temperature (PVT) variation using delay test. Using HSPICE with 65-nm and 45-nm gate libraries, this paper demonstrates that PVT variation has a negative impact on detectability of these two defects. To address this issue, this paper determines the appropriate voltage and temperature settings for detecting resistive open and bridge defects. This is identified by analyzing the timing critical resistance of these two defects under the combined effect of PVT variation. In addition, this work determines the most effective delay test class that achieves maximum coverage for resistive open defect.