DocumentCode
2052858
Title
SmartInjector: Exploiting intelligent fault injection for SDC rate analysis
Author
Jianli Li ; Qingping Tan
Author_Institution
Sch. of Comput., Nat. Univ. of Defense Technol., Changsha, China
fYear
2013
fDate
2-4 Oct. 2013
Firstpage
236
Lastpage
242
Abstract
Recently, researchers have shown that exploiting symptom-based solutions provides a promising way to achieve low-cost fault tolerance. However, these solutions cannot provide enough reliability due to lack of ability to handle silent data corruptions (SDCs). To address SDCs efficiently, it is important to identify them effectively. This paper presents an intelligent fault injection framework, SmartInjector, which can analyze the SDC rates of the instructions in an application accurately with affordable fault simulation efforts. Based on program analysis, SmartInjector firstly prunes the faults whose outcome can be known without fault simulation or the faults which are considered to be equivalent to other faults. SmartInjector also employs the fault outcome prediction technique to reduce the time for a single fault simulation. The decreased requirement of computational resources allows SmartInjector to perform detailed fault injection experiments to analyze SDC rate for each instruction in an application. Validation results show that the fault simulation time needed by SmartInjector is only about 0.15% of the time required for simulating all possible faults, while the analysis accuracy of SDC rate reaches to 94% on average. Unlike existing fault injection frameworks, SmartInjector is the first to exploit fault outcome prediction to reduce the single simulation time.
Keywords
fault simulation; fault tolerant computing; SDC rate analysis; SmartInjector; computational resources; fault injection frameworks; fault outcome prediction technique; fault simulation time; handle silent data corruptions; intelligent fault injection framework; program analysis; reliability; single fault simulation; symptom based solutions; Analytical models; Computational modeling; Fault tolerance; Fault tolerant systems; Predictive models; Registers; Transient analysis; Fault injection; Fault outcome prediction; Program analysis; Transient faults;
fLanguage
English
Publisher
ieee
Conference_Titel
Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2013 IEEE International Symposium on
Conference_Location
New York City, NY
ISSN
1550-5774
Print_ISBN
978-1-4799-1583-5
Type
conf
DOI
10.1109/DFT.2013.6653612
Filename
6653612
Link To Document