Exploiting error control approaches for Hardware Trojans on Network-on-Chip links

We exploit transient and permanent error control methods to address Hardware Trojan (HT) issues in Network-on-Chip (NoC) links. The use of hardware-efficient error control methods on NoC links has the potential to reduce the overall hardware cost for security protection, with respect to cryptographic-based rerouting algorithms. An error control coding method for transient errors is used to detect the HT-induced link errors. Regarding the faulty links as permanently failed interconnects, we propose to reshuffle the links and isolate the HT-controlled link wires. Rather than rerouting packets via alternative paths, the proposed method resumes the utilization of partially failed links to improve the bandwidth and the average latency of NoCs. Simulation results show that our method improves the average latency by up to 44.7% over the rerouting approach. The reduction on latency varies from 20% to 41% for three traffic patterns on a 5×5 mesh NoC. The impact of different HT locations on NoC links was examined, as well. Our method is not sensitive to HT locations and can improve the effective bandwidth by up to 29 bits per cycle with minor overhead.