On-chip error correction with unreliable decoders: Fundamental physical limits

Performance-power-area tradeoffs for on-chip error correction with unreliable decoders are considered from a physical-information-theoretic perspective. Fundamental upper bounds on information throughput under decoding power and heat removal constraints are obtained as a function of decoder efficacy for (n, k) linear block codes. Evaluation of these bounds is demonstrated for implementation of a (7,4) Hamming code in an illustrative example involving a classical bit-flip channel and a noisy decoder, and extension to codes with memory is briefly discussed. These bounds depend only on the statistical decoder input characteristics, the efficacy with which the decoder implements its intended function, and the decoder area; they are not derived from technology-specific assumptions about the decoder circuitry. As such, they can be used to explore tradeoffs between ultimate capabilities and resource requirements in the kinds of error correction scenarios that may be encountered in post-CMOS nanocomputing systems, where the decoding hardware designed to enhance reliability may itself be unreliable.