Reconfigurable distributed fault tolerant routing algorithm for on-chip networks

Network on chip (NoC) is emerging as a promising solution to overcome bus bottleneck for future multi core chips. Fault tolerance and quality of service issues are potential challenges for NoCs. In this paper, we propose a cost-effective fault tolerant routing algorithm for irregular 2D mesh without use of routing tables. We use one hop visibility of Logic Based Distributed Routing (LBDR) to eliminate routing tables. This algorithm handles one or multiple single link faults within 2D mesh and uses reconfigured paths (minimal and/or non-minimal), if links fail. We use turn model based approach to avoid deadlocks. Since our method does not require virtual channels to achieve deadlock freedom, it remains area and power efficient.