Testing of switch blocks in TSV-reduced Three-Dimensional FPGA

In recent years, density growth of VLSI system brings about increase of power consumption and routing delay, which comes to be a serious issue. Three-Dimensional (3D) IC technology is drawing attention as a solution. A 3D-FPGA is a new class of FPGA using the TSV (through silicon via) technology, one of 3D-IC technologies; the 3D-FPGA uses 3D switch blocks (SBs) in place of traditional 2D-SBs. In this term, constructions of a TSV-reduced 3D-FPGA were proposed, which use both 3D-SBs and 2D-SBs to reduce TSVs. Manufacturing testing method was proposed for the 3D-FPGA; however, this method targets 3D-FPGA with only 3D-SBs but no 2D-SBs, which provides redundant routing resources leading to a number of TSVs and large area overhead. This paper presents a built-in self-testing (BIST) for the TSV-reduced 3D-FPGA. This paper provides a placement of 3D-SBs to facilitate testing as a design for testing (DFT) and a test configuration for the proposed BIST. The evaluation results show that the number of required test configuration is 10.