LFSR-reseeding scheme for achieving test coverage

As the size and complexity of systems-on-chips continues to grow, the power dissipation during testing becomes very significant problem. During scan shifting, more transitions occur in the flip-flops compared to what occurs during normal functional operation. The proposed encoding scheme can be used in conjunction with partial LFSR reseeding scheme to significantly reduce test power and test storage. Encoding scheme act as the second stage of compression after LFSR reseeding. The number of transition in the scan chain can be reduced by filling the number of unspecified bits in different manner. And also it reduces the number of specified bits through LFSR reseeding to provide better encoding efficiency. This method can prevent all transitions in the non-transitional blocks and can reduce the number of specified bits for the non-transitional blocks.