DocumentCode
2053653
Title
On-demand transparency for improving hardware Trojan detectability
Author
Chakraborty, Rajat Subhra ; Paul, Somnath ; Bhunia, Swarup
Author_Institution
Dept. of Electr. Eng. & Comput. Sci., Case Western Reserve Univ., Cleveland, OH
fYear
2008
fDate
9-9 June 2008
Firstpage
48
Lastpage
50
Abstract
Malevolent Trojan circuits inserted by layout modifications in an IC at untrustworthy fabrication facilities are difficult to detect by traditional post-manufacturing testing. In this paper, we develop a novel low-overhead design methodology that facilitates the detection of inserted Trojan hardware in an IC through logic testing. As a byproduct, it also increases the security of the design by design obfuscation. Application of the proposed design methodology to an 8-bit RISC processor and a JPEG encoder resulted in improvement in Trojan detection probability significantly. It also obfuscated the design with verification mismatch for 90% of the verification points, while incurring moderate area, power and delay overheads.
Keywords
integrated circuit design; integrated circuit testing; logic testing; security of data; 8-bit RISC processor; IC layout modification; JPEG encoder; hardware Trojan detection probability; logic testing; low-overhead design methodology; on demand transparency; Circuit testing; Delay; Design methodology; Fabrication; Hardware; Integrated circuit layout; Integrated circuit testing; Logic testing; Reduced instruction set computing; Security; Design Obfuscation; Hardware Trojan Detection; Trust in IC;
fLanguage
English
Publisher
ieee
Conference_Titel
Hardware-Oriented Security and Trust, 2008. HOST 2008. IEEE International Workshop on
Conference_Location
Anaheim, CA
Print_ISBN
978-1-4244-2401-6
Type
conf
DOI
10.1109/HST.2008.4559048
Filename
4559048
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