Title :
In-system testing of cache memories
Author :
Sosnowski, Janusz
Author_Institution :
Inst. of Comput. Sci., Warsaw Univ. of Technol., Poland
Abstract :
Caches embedded in microprocessor systems are implemented with limited observability and controllability. Hence they create many problems in testing. This paper gives a methodology of developing user test programs for data and instruction caches with various organization
Keywords :
built-in self test; cache storage; computer testing; integrated circuit testing; microprocessor chips; cache memories; controllability; data caches; in-system testing; instruction caches; microprocessor systems; observability; user test programs; Built-in self-test; Cache memory; Circuit testing; Computer science; Logic arrays; Logic testing; Microprocessors; Observability; Read-write memory; System testing;
Conference_Titel :
Test Conference, 1995. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-2992-9
DOI :
10.1109/TEST.1995.529864
