Title :
Constructive multi-phase test point insertion for scan-based BIST
Author :
Tamarapalli, Nagesh ; Rajski, Janusz
Author_Institution :
Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada
Abstract :
This paper presents a novel test point insertion technique which, unlike the previous ones, is based on a constructive methodology. A divide and conquer approach is used to partition the entire test into multiple phases. In each phase a group of test points targeting a specific set of faults is selected. Control points within a particular phase are enabled by fixed values, resulting in a simple and natural sharing of the logic driving them. Experimental results demonstrate that complete or near-complete stuck-at fault coverage can be achieved by the proposed technique with the insertion of a few test points and a minimum number of phases
Keywords :
boundary scan testing; built-in self test; divide and conquer methods; fault diagnosis; integrated circuit testing; logic testing; constructive methodology; divide and conquer approach; fixed values; multi-phase test point insertion; near-complete stuck-at fault coverage; scan-based BIST; test points; Automatic test pattern generation; Built-in self-test; Circuit faults; Circuit simulation; Circuit testing; Costs; Graphics; Hardware; Laboratories; Logic;
Conference_Titel :
Test Conference, 1996. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-3541-4
DOI :
10.1109/TEST.1996.557122